The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

May. 13, 2011
Applicants:

Haizhou Yin, Poughkeepsie, NY (US);

Zhijong Luo, Poughkeepsie, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Inventors:

Haizhou Yin, Poughkeepsie, NY (US);

Zhijong Luo, Poughkeepsie, NY (US);

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/772 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26506 (2013.01); H01L 29/78 (2013.01); H01L 29/7848 (2013.01); H01L 29/41783 (2013.01);
Abstract

The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.


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