The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2015

Filed:

Mar. 04, 2011
Applicants:

Andrew Gabriel Rinzler, Gainesville, FL (US);

BO Liu, Gainesville, FL (US);

Mitchell Austin Mccarthy, Gainesville, FL (US);

Inventors:

Andrew Gabriel Rinzler, Gainesville, FL (US);

Bo Liu, Gainesville, FL (US);

Mitchell Austin McCarthy, Gainesville, FL (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 35/24 (2006.01); H01L 51/05 (2006.01); B82Y 10/00 (2011.01); H01L 51/00 (2006.01);
U.S. Cl.
CPC ...
H01L 51/0545 (2013.01); B82Y 10/00 (2013.01); H01L 51/0541 (2013.01); H01L 51/0591 (2013.01); H01L 51/0566 (2013.01); H01L 51/057 (2013.01); H01L 51/0048 (2013.01);
Abstract

Various embodiments are provided for semiconductor devices including an electrically percolating source layer and methods of fabricating the same. In one embodiment, a semiconductor device includes a gate layer, a dielectric layer, a memory layer, a source layer, a semiconducting channel layer, and a drain layer. The source layer is electrically percolating and perforated. The semiconducting channel layer is in contact with the source layer and the memory layer. The source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier.


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