The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Dec. 10, 2010
Applicants:

Deniz Balkan, Santa Clara, CA (US);

Kevin R. Walker, Los Gatos, CA (US);

Mitchell P. Lichtenberg, Jr., Sunnyvale, CA (US);

Inventors:

Deniz Balkan, Santa Clara, CA (US);

Kevin R. Walker, Los Gatos, CA (US);

Mitchell P. Lichtenberg, Jr., Sunnyvale, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31705 (2013.01); G01R 31/31727 (2013.01);
Abstract

A debug port configured to generate and provide a return clock is disclosed. In one embodiment, an integrated circuit (IC) includes one or more functional units and a debug port (DP). The DP is configured to enable access by an external debugger to the functional unit(s) of the IC for debugging purposes. The DP includes circuitry that may generate a first clock signal that is provided to the functional unit(s) during debug operations. Receiving test result data at the DP may require a return clock signal that is not provided by the functional unit(s). Accordingly, the IC may include a clock modifier coupled to receive the first clock signal. The clock modifier may generate a second clock signal based on the first, the second clock signal being provided to the DP as a return clock signal.


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