The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Mar. 26, 2012
Applicants:

Kalyana Krishnan, Hyderabad, IN;

Hai-jo Tarn, San Jose, CA (US);

Inventors:

Kalyana Krishnan, Hyderabad, IN;

Hai-Jo Tarn, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/13 (2006.01); H03M 13/11 (2006.01); H03M 13/05 (2006.01); H03M 13/21 (2006.01); H03M 13/15 (2006.01);
U.S. Cl.
CPC ...
H03M 13/13 (2013.01); H03M 13/1134 (2013.01); H03M 13/1137 (2013.01); H03M 13/05 (2013.01); H03M 13/21 (2013.01); H03M 13/134 (2013.01); H03M 13/6561 (2013.01); H03M 13/1171 (2013.01); H03M 13/1515 (2013.01); H03M 13/6502 (2013.01);
Abstract

An encoder module includes P/L parity shift registers that are sequentially coupled, wherein an input of a first parity shift register of the parity shift registers is coupled to the input of the encoder module, an output of the last parity shift register of the parity shift registers is coupled to the output of the encoder module, each of the parity shift registers being configured to store L parity digits. The encoder module also includes a feedback circuit comprising P/L parity generation modules, wherein each of the parity generation modules is coupled to an output of a corresponding one of the parity shift registers by a switch and also coupled to the input of the first parity shift register, wherein each of the parity generation modules is configured to generate L parity digits for transmission to the input of the first parity shift register when its corresponding switch is closed.


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