The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Apr. 29, 2011
Applicants:

Edward M. Mccombs, Austin, TX (US);

Chetan C. Kamdar, Austin, TX (US);

William V. Miller, Austin, TX (US);

Inventors:

Edward M. McCombs, Austin, TX (US);

Chetan C. Kamdar, Austin, TX (US);

William V. Miller, Austin, TX (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); H03K 19/096 (2006.01); G06F 12/10 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
H03K 19/096 (2013.01); G11C 7/062 (2013.01); G06F 12/1027 (2013.01);
Abstract

A processor includes a translation lookaside buffer (TLB) including a data array and a compare unit. The data array includes a number of entries each configured to store a respective translated physical address. In response to a read access to a given entry of the TLB, the data array is configured to output within a particular clock cycle, the respective translated physical address stored in the given entry. In addition the compare unit may be configured to compare the respective translated physical address output by the data array with a number of additional addresses. The compare unit may also be configured to provide a hit indication for each of the additional addresses within the particular clock cycle.


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