The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Oct. 16, 2009
Applicants:

Yasuhiko Kurosawa, Kanagawa, JP;

Shigeaki Iwasa, Kanagawa, JP;

Seiji Maeda, Kanagawa, JP;

Nobuhiro Yoshida, Tokyo, JP;

Mitsuo Saito, Kanagawwa, JP;

Hiroo Hayashi, Kanagawa, JP;

Inventors:

Yasuhiko Kurosawa, Kanagawa, JP;

Shigeaki Iwasa, Kanagawa, JP;

Seiji Maeda, Kanagawa, JP;

Nobuhiro Yoshida, Tokyo, JP;

Mitsuo Saito, Kanagawwa, JP;

Hiroo Hayashi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/10 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1054 (2013.01);
Abstract

An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.


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