The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Oct. 31, 2010
Applicants:

Mohammad Shahanshah Akhter, Ottawa, CA;

Zixiong William Wang, Ottawa, CA;

David Clifton Bond, Ottawa, CA;

Gregory Edward Lund, Eau Claire, WI (US);

Inventors:

Mohammad Shahanshah Akhter, Ottawa, CA;

Zixiong William Wang, Ottawa, CA;

David Clifton Bond, Ottawa, CA;

Gregory Edward Lund, Eau Claire, WI (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/861 (2013.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); H04L 49/90 (2013.01);
Abstract

A method and apparatus for a configurable packet routing, buffering and scheduling scheme to optimize throughput with deadlock prevention in SRIO-to-PCIe Bridges have been described. A single level enqueue method with dynamic buffering and dequeuing based on packet re-ordering is disclosed. Single level packet routing and scheduling to meet SRIO and PCIe rules to enqueue packets based on FType/TType is disclosed. Backpressure based on ingress watermarks for different packet types is disclosed. Use of a circular-reorder queue (CRQ) for both ingress and egress allows packet reordering and packet passing.


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