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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8949101 B1

PDFFull Text
Date of Patent:
Feb. 03, 2015

Filed:

Oct. 12, 2011

Hardware execution driven application level derating calculation for soft error rate analysis

Applicants:

Pradip Bose, Yorktown Heights, NY (US);

Meeta S. Gupta, White Plains, NY (US);

Prabhakar N. Kudva, New York, NY (US);

Daniel A. Prener, Croton-on-Hudson, NY (US);

Inventors:

Pradip Bose, Yorktown Heights, NY (US);

Meeta S. Gupta, White Plains, NY (US);

Prabhakar N. Kudva, New York, NY (US);

Daniel A. Prener, Croton-on-Hudson, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Stephen R. Tkacs

Stephen J. Walder, Jr.

Jennifer R. Davis

Primary Examiner:

Kamini S Shah

Assistant Examiner:

Michael P Healey

Int. Cl.
CPC ...
G01R 31/3181 (2006.01); G06F 17/50 (2006.01); G01R 31/3183 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31816 (2013.01); G01R 31/318357 (2013.01); G06F 17/5022 (2013.01);
Abstract

Mechanisms are provided for predicting effects of soft errors on an integrated circuit device design. A data processing system is configured to implement a unified derating tool that includes a machine derating front-end engine used to generate machine derating information, and an application derating front-end engine used to generate application derating information, for the integrated circuit device design. The machine derating front-end engine executes a simulation of the integrated circuit device design to generate the machine derating information. The application derating front-end engine executes an application workload on existing hardware similar in architecture to the integrated circuit device design and injects a fault into the existing hardware during execution of the application workload to generate application derating information. The machine derating information is combined with the application derating information to generate at least one soft error rate value for the integrated circuit device design.

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