The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2015
Filed:
Jul. 29, 2011
Applicants:
Jia Feng, San Jose, CA (US);
Zhi-yuan Wu, Union City, CA (US);
Juhi Bansal, Sunnyvale, CA (US);
Srinath Krishnan, Campbell, CA (US);
Inventors:
Jia Feng, San Jose, CA (US);
Zhi-Yuan Wu, Union City, CA (US);
Juhi Bansal, Sunnyvale, CA (US);
Srinath Krishnan, Campbell, CA (US);
Assignee:
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01);
Abstract
A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.