The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2015
Filed:
Oct. 09, 2012
Freescale Semiconductor, Inc., Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
In accordance with at least one embodiment, a non-volatile memory (NVM) and method is disclosed for detecting latent slow erase bits. At least a portion of an array of NVM cells is erased with a reduced erase bias. The reduced erase bias has a reduced level relative to a normal erase bias. A least erased bit (LEB) threshold voltage level of the least erased bit (LEB) is determined. An erase verify is performed at an adjusted erase verify read threshold voltage level. The adjusted erase verify read threshold voltage level is a predetermined amount lower than the LEB read threshold voltage level. A number of failing bits is determined. The failing bits are bits with a threshold voltage above the adjusted erase verify level. The NVM is rejected in response to the number of failing bits being less than a failing bits threshold.