The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2015
Filed:
Mar. 04, 2011
Applicants:
Dae-suk Kim, Gyeonggi-do, KR;
Jong-chern Lee, Gyeonggi-do, KR;
Chul Kim, Gyeonggi-do, KR;
Inventors:
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/80 (2006.01); H01L 23/48 (2006.01); H01L 21/66 (2006.01); G01R 31/28 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); G01R 31/2853 (2013.01); H01L 23/481 (2013.01); G01R 31/2884 (2013.01); H01L 24/05 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06596 (2013.01);
Abstract
An integrated circuit that detects whether a through silicon via has defects or not, at a wafer level. The integrated circuit includes a semiconductor substrate, a through silicon via configured to be formed in the semiconductor substrate to extend to a certain depth from the surface of the semiconductor substrate, an output pad, and a current path providing unit configured to provide a current, flowing between the semiconductor substrate and the through silicon via, to the output pad during a test mode.