The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Oct. 30, 2012
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Vitor M. Pereira, Austin, TX (US);

Trent O. Dudley, Peckville, PA (US);

Jessica P. Davis, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

On-chip decoupling capacitors and methods for placing the same are disclosed in which designated spaces are created between the active circuits to insert designated capacitor cells. The designated capacitor cells may be placed in designated areas of the integrated circuit that are not simply spaces left empty by cell placement or frontier areas in or around the route, and the dimensions (e.g., height) of the designated capacitor cells may be selected to optimize (increase) capacitance efficiency. The capacitor cells may also be placed to target and reduce the interference between a digital core (aggressor) circuit and a victim analog circuit.


Find Patent Forward Citations

Pereira, Vitor. (2015). Decoupling capacitors for integrated circuits (U.S. Patent No. 8946856). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8946856

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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