The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Feb. 20, 2007
Applicants:

Peter Rabkin, Cupertino, CA (US);

Hsingya Arthur Wang, San Jose, CA (US);

Kai-cheng Chou, San Jose, CA (US);

Inventors:

Peter Rabkin, Cupertino, CA (US);

Hsingya Arthur Wang, San Jose, CA (US);

Kai-Cheng Chou, San Jose, CA (US);

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8232 (2006.01); H01L 21/8234 (2006.01); H01L 27/115 (2006.01); H01L 27/105 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); H01L 21/823418 (2013.01); H01L 21/823468 (2013.01); H01L 27/105 (2013.01); H01L 27/11546 (2013.01); H01L 29/42324 (2013.01);
Abstract

A semiconductor transistor is formed as follows. A gate electrode is formed over but is insulated from a semiconductor body region. A first layer of insulating material is formed over the gate electrode and the semiconductor body region. A second layer of insulating material different from the first layer of insulating material is formed over the first layer of insulating material. Only the second layer of insulating material is etched to form spacers along the side-walls of the gate electrode. Impurities are implanted through the first layer of insulating material to form a source region and a drain region in the body region. A substantial portion of those portions of the first layer of insulting material extending over the source and drain regions is removed.


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