The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Jun. 17, 2013
Applicant:

Advanced Optoelectronic Technology, Inc., Hsinchu Hsien, TW;

Inventors:

Pin-Chuan Chen, Hsinchu, TW;

Chao-Hsiung Chang, Hsinchu, TW;

Hsin-Chiang Lin, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/60 (2010.01); H01L 33/52 (2010.01); H01L 33/48 (2010.01); H01L 33/62 (2010.01); H01L 33/54 (2010.01);
U.S. Cl.
CPC ...
H01L 33/60 (2013.01); H01L 33/52 (2013.01); H01L 33/486 (2013.01); H01L 33/62 (2013.01); H01L 33/54 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/8592 (2013.01);
Abstract

A method for manufacturing an LED (light emitting diode) is disclosed wherein a metal substrate is provided. A chip fastening area with a depression and two wire fixing areas on the first metal substrate are defined on the metal substrate. The chip fastening area and the wire fixing areas are separated by a plurality of first grooves. An LED chip is provided in the depression of the chip fastening area and electrically connected to the wire fixing areas by wires. An encapsulant is formed to cover and connect the chip fastening area and the wire fixing areas. Portions of the metal substrate except the chip fastening area and the wire fixing areas are removed.


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