The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Jan. 02, 2014
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Keiji Tomizawa, Yokohama, JP;

Chiaki Muraoka, Kawaguchi, JP;

Takuma Kodoi, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B41J 2/16 (2006.01); B41J 2/145 (2006.01);
U.S. Cl.
CPC ...
B41J 2/1631 (2013.01); B41J 2/145 (2013.01);
Abstract

A process for producing a chip in which plural ejection orifice arrays are arranged including conducting reduction projection exposure plural times to a wafer having a substrate and a photosensitive resin layer formed thereon while relatively moving positions of the wafer and a reticle to form ejection orifice array patterns in the resin layer, developing the patterns to form ejection orifice arrays in the resin layer, and dividing the wafer to form plural chips in which the plural ejection orifice arrays are arranged. The exposure is conducted once to form in the resin layer a first ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip, a second ejection orifice array pattern corresponding to all ejection orifice arrays in one chip and a third ejection orifice array pattern corresponding to partial ejection orifice arrays in an arranging direction thereof in one chip.


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