The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Dec. 17, 2010
Applicants:

Rotem Oshman, Cambridge, MA (US);

John R. Douceur, Bellevue, WA (US);

Thomas Moscibroda, Redmond, WA (US);

Inventors:

Rotem Oshman, Cambridge, MA (US);

John R. Douceur, Bellevue, WA (US);

Thomas Moscibroda, Redmond, WA (US);

Assignee:

Microsoft Corporation, Redmond, WA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/52 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/526 (2013.01); G06F 11/1479 (2013.01); G06F 2201/825 (2013.01);
Abstract

Techniques for implementing mutual-exclusion algorithms that are also fault-resistant are described herein. For instance, this document describes systems that implement fault-resistant, mutual-exclusion algorithms that at least prevent simultaneous access of a shared resource by multiple threads when (i) one of the multiple threads is in its critical section, and (ii) the other thread(s) are waiting in a loop to enter their respective critical sections. In some instances, these algorithms are fault-tolerant to prevent simultaneous access of the shared resource regardless of a state of the multiple threads executing on the system. In some instances, these algorithms may resist (e.g., tolerate entirely) transient memory faults (or 'soft errors').


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