The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Aug. 15, 2012
Applicants:

Michael W. Harper, Round Rock, TX (US);

Mack W. Riley, Austin, TX (US);

Inventors:

Michael W. Harper, Round Rock, TX (US);

Mack W. Riley, Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/00 (2006.01); G06F 11/00 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G01R 31/317 (2006.01); G06F 11/27 (2006.01); G06F 11/25 (2006.01); G06F 11/30 (2006.01); G06F 11/34 (2006.01); G11C 29/12 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/318533 (2013.01); G01R 31/318544 (2013.01); G01R 31/318566 (2013.01); G01R 31/3187 (2013.01); G01R 31/317 (2013.01); G01R 31/31724 (2013.01); G01R 31/318555 (2013.01); G01R 31/2856 (2013.01); G01R 31/2851 (2013.01); G06F 11/27 (2013.01); G06F 11/25 (2013.01); G06F 11/3003 (2013.01); G06F 11/3065 (2013.01); G06F 11/3089 (2013.01); G06F 11/3466 (2013.01); G11C 29/12 (2013.01);
Abstract

An integrated circuit includes an LBIST controller operative to run a test program on at least one selection of core logic of the integrated circuit to test the operability of the at least one selection of core logic. The integrated circuit also includes a monitoring logic structure operative to detect at least one type of operation executed for the test program from at least one particular control signal activated by the LBIST controller for controlling the at least one selection of core logic to execute the test program from among at least one control signal for controlling operations on the at least one selection of core logic.


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