The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Aug. 16, 2012
Applicants:

Bradley M. Waters, Woodinville, WA (US);

Danyu Zhu, Redmond, WA (US);

Inventors:

Bradley M. Waters, Woodinville, WA (US);

Danyu Zhu, Redmond, WA (US);

Assignee:

Microsoft Corporation, Redmond, WA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/24 (2006.01); G06F 9/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4843 (2013.01);
Abstract

Various embodiments provide an ability to schedule latency-sensitive tasks based, at least in part, upon one or more processor cores usage metrics. Some embodiments gather information associated with whether one or more processor cores are in a heavily loaded state. Alternately or additionally, some embodiments gather information identifying latency-sensitive tasks. Task(s) can be (re)assigned to different processor core(s) for execution when it has been determined that an originally assigned processor core has exceeded a usage threshold.


Find Patent Forward Citations

Waters, Bradley. (2015). Latency sensitive software interrupt and thread scheduling (U.S. Patent No. 8943252). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8943252

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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