The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Mar. 23, 2011
Applicants:

Yiran Chen, Eden Prairie, MN (US);

Dadi Setiadi, Edina, MN (US);

Patrick J. Ryan, St. Paul, MN (US);

Inventors:

Yiran Chen, Eden Prairie, MN (US);

Dadi Setiadi, Edina, MN (US);

Patrick J. Ryan, St. Paul, MN (US);

Assignee:

Seagate Technology LLC, Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 11/16 (2006.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 11/161 (2013.01); G11C 7/1006 (2013.01); G11C 11/5607 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 2211/5648 (2013.01);
Abstract

Apparatus and method for managing an array of multi-level cell (MLC) memory cells. In accordance with various embodiments, a non-sequential encoding scheme is selected that assigns a different multi-bit logical value to each of a plurality of available physical states of a selected MLC memory cell in relation to write effort associated with each of said plurality of physical states. Data are thereafter written to the selected MLC memory cell in relation to the selected non-sequential encoding scheme. In some embodiments, the MLC memory cell comprises a spin-torque transfer random access memory (STRAM) memory cell. In other embodiments, the MLC memory cell comprises an MLC flash memory cell.


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