The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Jul. 10, 2013
Applicant:

Electronics and Telecommunications Research Institute, Daejeon, KR;

Inventors:

Young Rak Park, Daejeon, KR;

Sang Choon Ko, Daejeon, KR;

Byoung-Gue Min, Daejeon, KR;

Jong-Won Lim, Daejeon, KR;

Hokyun Ahn, Daejeon, KR;

Sung-Bum Bae, Daejeon, KR;

Jae Kyoung Mun, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 29/66 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66477 (2013.01); H01L 23/5225 (2013.01); H01L 23/5329 (2013.01); H01L 23/66 (2013.01); H01L 23/5228 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Provided are an electronic chip and a method of fabricating the same. The semiconductor chip may include a substrate, an active device integrated on the substrate, a lower interlayered insulating layer covering the resulting structure provided with the active device, a passive device provided on the lower interlayered insulating layer, an upper interlayered insulating layer covering the resulting structure provided with the passive device, and a ground electrode provided on the upper interlayered insulating layer. The upper interlayered insulating layer may be formed of a material, whose dielectric constant may be higher than that of the lower interlayered insulating layer.


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