The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2015

Filed:

Nov. 01, 2011
Applicants:

Okifumi Nakagawa, Osaka, JP;

Yoshimasa Chikama, Osaka, JP;

Takeshi Hara, Osaka, JP;

Hiromitsu Katsui, Osaka, JP;

Inventors:

Okifumi Nakagawa, Osaka, JP;

Yoshimasa Chikama, Osaka, JP;

Takeshi Hara, Osaka, JP;

Hiromitsu Katsui, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 29/66 (2006.01); G02F 1/1362 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66969 (2013.01); G02F 1/136227 (2013.01); H01L 27/1225 (2013.01); H01L 29/7869 (2013.01); H01L 29/41733 (2013.01); H01L 29/66742 (2013.01); H01L 29/78606 (2013.01); G02F 2001/136231 (2013.01);
Abstract

The semiconductor device () according to the present invention includes a gate electrode () of a TFT, a gate insulating layer () formed on the gate electrode (), an oxide semiconductor layer () disposed on the gate insulating layer (), a protecting layer () formed on the oxide semiconductor layer () by a spin-on-glass technique, and a source electrode () and a drain electrode () disposed on the protecting layer (). Via a first contact hole () formed in the protecting layer (), the source electrode () is electrically connected to the oxide semiconductor layer (), and via a second contact hole (), the drain electrode () is electrically connected to the oxide semiconductor layer ().


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