Staggered power-up and synchronized reset for a large asic or fpga

Abstract

Methods and apparatus for controlling the power-on current transients and for providing a gradual current draw in an ASIC or FPGA having a high gate count and a number of physical blocks are disclosed. Additionally, method(s) are disclosed which ensure related blocks emerge from a reset state on a common clock cycle even when the related blocks are geographically dispersed over a large area producing multiple clock cycle latency periods for signals between blocks. Complete flexibility of physical block start up is achieved by software control which permits the sequence and number of physical blocks started simultaneously.