The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8937831 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 20, 2015

Filed:

Jan. 14, 2013
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Moon-Hae Son, San Jose, CA (US);

Peter Lee, Pleasanton, CA (US);

Winston Lee, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/22 (2006.01); G11C 11/419 (2006.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 7/08 (2013.01); G11C 7/227 (2013.01); G11C 11/419 (2013.01);
Abstract

Systems, methods, and other embodiments associated with controlling a sense amplifier in a memory device are described. According to one embodiment, an apparatus includes a signal generator configured to generate a sense enable signal that activates a sense amplifier of a memory cell in a memory device. The apparatus includes a dummy memory cell connected to a current mirror circuit that is configured to detect a timing variation in the dummy memory cell from a predefined timing and to alter a timing of the sense enable signal based, at least in part, on the timing variation. The apparatus also includes a controller configured to modify the timing of the sense enable signal by selectively enabling one or more of a plurality of semiconductor gates in the current mirror circuit. The plurality of semiconductor gates are connected in parallel.


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