The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8937256 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 20, 2015

Filed:

Jan. 19, 2012
Applicants:

Masahiro Inoue, Konan, JP;

Hajime Saiki, Konan, JP;

Atsuhiko Sugimoto, Kagamigahara, JP;

Inventors:

Masahiro Inoue, Konan, JP;

Hajime Saiki, Konan, JP;

Atsuhiko Sugimoto, Kagamigahara, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01K 1/02 (2006.01); H05K 13/04 (2006.01); H05K 3/34 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H05K 3/3478 (2013.01); H01L 24/81 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10977 (2013.01); H01L 2224/16225 (2013.01);
Abstract

A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.


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