The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Nov. 19, 2012
Applicants:

Guoping Wan, Suzhou, CN;

Shayan Zhang, Suzhou, CN;

Wanggen Zhang, Suzhou, CN;

Inventors:

Guoping Wan, Suzhou, CN;

Shayan Zhang, Suzhou, CN;

Wanggen Zhang, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G11C 29/32 (2006.01); G01R 31/3187 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318536 (2013.01); G11C 29/32 (2013.01); G01R 31/3187 (2013.01); G01R 31/318558 (2013.01);
Abstract

A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.


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