The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

May. 22, 2012
Applicants:

Hongshin Jun, San Jose, CA (US);

William Eklow, San Jose, CA (US);

Sun-gyu Kim, Pleasanton, CA (US);

Inventors:

Hongshin Jun, San Jose, CA (US);

William Eklow, San Jose, CA (US);

Sun-Gyu Kim, Pleasanton, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.


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