The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Dec. 07, 2011
Applicants:

Daehyun Nam, Goyang-si, KR;

Dosung Kim, Goyang-si, KR;

Sunghak JO, Goyang-si, KR;

Seonghun Jeong, Paju-si, KR;

Inventors:

Daehyun Nam, Goyang-si, KR;

Dosung Kim, Goyang-si, KR;

Sunghak Jo, Goyang-si, KR;

Seonghun Jeong, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/00 (2006.01); G09G 3/00 (2006.01); G09G 3/36 (2006.01); G11C 19/28 (2006.01); H04N 13/04 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 3/003 (2013.01); G09G 3/3659 (2013.01); G11C 19/28 (2013.01); H04N 13/0434 (2013.01); H04N 13/0452 (2013.01); H04N 13/0497 (2013.01); G09G 3/20 (2013.01); G09G 3/3677 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0443 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01);
Abstract

Embodiments of the invention relate to a stereoscopic image display and a method for driving the same. Stereoscopic image display includes a data display unit including a first scan transistor, an active black stripe unit including a second transistor and a third transistor, and a shift register sequentially supplying the gate pulse to each of (2n−1)th gate lines and (2n)th gate lines, where n is a natural number. The first scan transistor supplies a data voltage to a pixel electrode in response to a gate pulse of a (2n−1)th gate line, the second transistor supplies the data voltage to the pixel electrode in response to the gate pulse of the (2n−1)th gate line, and the third transistor supplies a low logic level voltage or a common voltage to the pixel electrode in response to a gate pulse of a (2n)th gate line.


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