The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Sep. 14, 2012
Applicants:

Sunwon Kang, Seongnam-si, KR;

Chiwook Kim, Hwaseong-si, KR;

Hyun Jeong Woo, Hwaseong-si, KR;

Sangjoon Hwang, Seoul, KR;

Inventors:

SunWon Kang, Seongnam-si, KR;

Chiwook Kim, Hwaseong-si, KR;

Hyun jeong Woo, Hwaseong-si, KR;

Sangjoon Hwang, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 3/00 (2006.01); H02M 1/14 (2006.01); H01L 23/64 (2006.01); G11C 11/4074 (2006.01);
U.S. Cl.
CPC ...
H01L 23/642 (2013.01); G11C 11/4074 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.


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