The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 13, 2015

Filed:

Dec. 01, 2011
Applicants:

Aneesh Nainani, Palo Alto, CA (US);

Krishna Chandra Saraswat, Saratoga, CA (US);

Inventors:

Aneesh Nainani, Palo Alto, CA (US);

Krishna Chandra Saraswat, Saratoga, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/80 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 29/66462 (2013.01); H01L 29/802 (2013.01); H01L 2924/10348 (2013.01); H01L 21/02395 (2013.01); H01L 21/02466 (2013.01); H01L 21/02502 (2013.01); H01L 21/02549 (2013.01); H01L 29/517 (2013.01);
Abstract

In accordance with one or more embodiments, an apparatus and method involves a channel region, barrier layers separated by the channel region and a dielectric on one of the barrier layers. The barrier layers have band gaps that are different than a band gap of the channel region, and confine both electrons and holes in the channel region. A gate electrode applies electric field to the channel region via the dielectric. In various contexts, the apparatus and method are amenable to implementation for both electron-based and hole-based implementations, such as for nmos, pmos, and cmos applications.


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