The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8933394 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 13, 2015

Filed:

Feb. 23, 2011
Applicants:

Hiroshi Okada, Mie, JP;

Takuya Sunada, Osaka, JP;

Takeshi Oomori, Osaka, JP;

Inventors:

Hiroshi Okada, Mie, JP;

Takuya Sunada, Osaka, JP;

Takeshi Oomori, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 5/02 (2006.01); H01L 29/06 (2006.01); H03K 17/687 (2006.01); H01L 25/16 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H03K 17/785 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66068 (2013.01); H01L 29/0696 (2013.01); H03K 2217/0009 (2013.01); H03K 17/6874 (2012.01); H01L 29/1608 (2013.01); H01L 29/0619 (2013.01); H01L 25/167 (2013.01); H01L 29/7811 (2013.01); H03K 17/785 (2013.01);
Abstract

A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode.


Find Patent Forward Citations

Okada, Hiroshi. (2015). Semiconductor device having at least a transistor cell with a second conductive type region surrounding a wall region and being insulated from both gate electrode and source electrode and solid state relay using same (U.S. Patent No. 8933394). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8933394

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…