The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Mar. 30, 2011
Applicants:

Ikuo Ohtsuka, Kawasaki, JP;

Eiichi Konno, Kawasaki, JP;

Takahiko Orita, Kawasaki, JP;

Yoshitaka Nishio, Kawasaki, JP;

Toshiyasu Sakata, Kawasaki, JP;

Inventors:

Ikuo Ohtsuka, Kawasaki, JP;

Eiichi Konno, Kawasaki, JP;

Takahiko Orita, Kawasaki, JP;

Yoshitaka Nishio, Kawasaki, JP;

Toshiyasu Sakata, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01);
Abstract

A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.


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