The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Oct. 03, 2012
International Business Machines Corporation, Armonk, NY (US);
Debjit Sinha, Wappinger Falls, NY (US);
Eric J. Fluhr, Round Rock, TX (US);
Stephen G. Shuma, Underhill, VT (US);
Natesan Venkateswaran, Hopewell Junction, NY (US);
Chandramouli Visweswariah, Croton-on-Hudson, NY (US);
Michael H. Wood, Hopewell Junction, NY (US);
Vladimir Zolotov, Putnam Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and a system for timing analysis of a VLSI circuit or chip design considering manufacturing and environmental variations, where the design includes multiple instances of a gate or macro instantiated at more than one voltage domain by sharing and re-using abstracts. The timing analysis of the chip includes a macro abstract instantiated in a voltage domain different from the domain during abstract generation. Timing models are re-used across chip voltage domains or across chip designs. Moreover, a statistical timing analysis of a chip design takes into consideration the voltage domains wherein at least one timing abstract model generation time voltage domain condition differs from the macro instantiation domain in the chip. The invention further provides sharing and re-using the statistical timing models or abstracts.