The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jun. 07, 2012
Applicant:

Hironobu Taoka, Kanagawa, JP;

Inventor:

Hironobu Taoka, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/36 (2012.01); G03F 1/70 (2012.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G03F 1/70 (2013.01); G06F 17/5081 (2013.01);
Abstract

A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.


Find Patent Forward Citations

Taoka, Hironobu. (2015). Mask data verification apparatus, design layout verification apparatus, method thereof, and computer program thereof (U.S. Patent No. 8930857). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8930857

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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