The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Jul. 20, 2012
Joel James Mccormack, Boulder, CO (US);
Rajesh Kota, Austin, TX (US);
Olivier Giroux, San Jose, CA (US);
Emmett M. Kilgariff, San Jose, CA (US);
Joel James McCormack, Boulder, CO (US);
Rajesh Kota, Austin, TX (US);
Olivier Giroux, San Jose, CA (US);
Emmett M. Kilgariff, San Jose, CA (US);
NVIDIA Corporation, Santa Clara, CA (US);
Abstract
One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.