The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Oct. 19, 2012
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sanjeev Ghai, Round Rock, TX (US);

Guy L. Guthrie, Austin, TX (US);

William J. Starke, Round Rock, TX (US);

Jeff A. Stuecheli, Austin, TX (US);

Derek E. Williams, Austin, TX (US);

Phillip G. Williams, Leander, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2006.01); G06F 12/12 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0817 (2013.01); G06F 12/0804 (2013.01); G06F 12/121 (2013.01); G06F 12/122 (2013.01);
Abstract

In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.


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