The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Jan. 20, 2011
Raymond G Beausoleil, Redmond, WA (US);
Marco Fiorentino, Mountain View, CA (US);
Moray Mclaren, Bristol, GB;
Greg Astfalk, Parker, TX (US);
Nathan Lorenzo Binkert, Redwood City, CA (US);
David A. Fattal, Mountain View, CA (US);
Raymond G Beausoleil, Redmond, WA (US);
Marco Fiorentino, Mountain View, CA (US);
Moray McLaren, Bristol, GB;
Greg Astfalk, Parker, TX (US);
Nathan Lorenzo Binkert, Redwood City, CA (US);
David A. Fattal, Mountain View, CA (US);
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Abstract
In one example, a composite processor includes a circuit board, a first processor element package, and a second processor element package. The circuit board has an optical link and an electrical link. The first processor element package includes a substrate with an integrated circuit, a sub-wavelength grating optical coupler, and an electrical coupler coupled to the electrical link of the circuit board. The second processor element package includes a substrate with an integrated circuit, a sub-wavelength grating optical coupler, and an electrical coupler coupled to the electrical link of the circuit board. The sub-wavelength grating optical coupler of the first processor element package, the optical link of the circuit board, and the sub-wavelength grating optical coupler of the second processor element package collectively define an optical communications path between the substrate of the first processor element package and the substrate of the second processor element package.