The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jul. 27, 2012
Applicants:

Ryo Endo, Kanagawa, JP;

Keisuke Ueda, Kanagawa, JP;

Toshiya Uozumi, Kanagawa, JP;

Inventors:

Ryo Endo, Kanagawa, JP;

Keisuke Ueda, Kanagawa, JP;

Toshiya Uozumi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/06 (2006.01); H04L 27/00 (2006.01); H03K 23/66 (2006.01);
U.S. Cl.
CPC ...
H03K 23/662 (2013.01); H04L 27/0014 (2013.01); H04L 2027/0036 (2013.01); H04L 2027/0022 (2013.01); H04L 2027/0055 (2013.01); H04L 2027/0087 (2013.01); H04L 2027/0016 (2013.01); H04L 2027/0067 (2013.01); H04L 2027/0069 (2013.01);
Abstract

To reduce the influence of a spurious in a high-frequency signal processing device and a wireless communication system each provided with a digital type PLL circuit. In a digital type PLL circuit including a digital phase comparator unit, a digital low-pass filter, a digital control oscillator unit, and a multi-module driver unit (frequency divider unit), the clock frequency of a clock signal in the digital phase comparator unit is configured selectably among a plurality of options. The clock frequency is selected among frequencies which are integer multiples of a reference frequency, in accordance with which frequency band of a standard is to be set for an oscillation output signal of the digital control oscillator unit.


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