The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jul. 31, 2013
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Kent Jaeger, Cary, IL (US);

Lawrence E. Connell, Naperville, IL (US);

Daniel P. McCarthy, Elk Grove Village, IL (US);

Brian T. Creed, Batavia, IL (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/10 (2006.01); H03B 19/00 (2006.01); H03K 3/353 (2006.01);
U.S. Cl.
CPC ...
H03K 3/353 (2013.01);
Abstract

An apparatus comprising a frequency divider comprising a first latch and a second latch coupled to the first latch in a toggle-flop configuration, and an output circuit comprising a first p-channel transistor, wherein the gate of the first p-channel transistor is configured to receive a clock signal, a first n-channel transistor, wherein the gate of the first n-channel transistor is coupled to the first latch, a second n-channel transistor connected in series with the first p-channel transistor and the first n-channel transistor and wherein the gate of the second n-channel transistor is configured to receive the clock signal, a second p-channel transistor, wherein the gate of the second p-channel transistor is configured to receive the clock signal, and a third n-channel transistor in series with the second p-channel transistor and the second n-channel transistor, wherein the output circuit is configured to generate a pair of in-phase reference signals.


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