The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Sep. 30, 2011
Applicants:

Ayumu Hatanaka, Tokyo, JP;

Kaoru Kato, Tokyo, JP;

Katsumi Ishikawa, Tokyo, JP;

Naoki Maru, Tokyo, JP;

Inventors:

Ayumu Hatanaka, Tokyo, JP;

Kaoru Kato, Tokyo, JP;

Katsumi Ishikawa, Tokyo, JP;

Naoki Maru, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/00 (2006.01); H03K 3/012 (2006.01); H01L 27/06 (2006.01); H02M 1/08 (2006.01); H02M 1/38 (2007.01);
U.S. Cl.
CPC ...
H03K 3/012 (2013.01); H01L 27/0629 (2013.01); H02M 1/08 (2013.01); H02M 1/38 (2013.01); Y02B 70/1483 (2013.01);
Abstract

The dead time is secured stably in a semiconductor drive circuit for switching devices using a wide band gap semiconductor. The drain terminal of the switching device of an upper arm is connected to the positive terminal of a first power supply, the source terminal of the switching device of a lower arm is connected to the negative terminal of the first power supply, and the source terminal of the switching device of the upper arm is connected with the drain terminal of the switching device of the lower arm. A gate drive circuit provided for each switching device includes an FET circuit and a parallel circuit made of a parallel connection of a first resistor and a first capacitor and having a first terminal connected to the gate terminal of the switching device.


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