The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Sep. 07, 2012
Applicants:

Liang-teck Pang, White Plains, NY (US);

Joel A. Silberman, Somers, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Inventors:

Liang-Teck Pang, White Plains, NY (US);

Joel A. Silberman, Somers, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); G01R 31/3185 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318558 (2013.01); G01R 31/318513 (2013.01); G01R 31/318572 (2013.01); H01L 25/0657 (2013.01);
Abstract

There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.


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