The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Jul. 19, 2012
Applicant:

Ichirou Matsuo, Kyoto, JP;

Inventor:

Ichirou Matsuo, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 27/115 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/861 (2006.01); H01L 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/94 (2013.01); H01L 27/11521 (2013.01); H01L 27/11558 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01); H01L 29/8611 (2013.01); H01L 27/0629 (2013.01);
Abstract

A memory device includes a MISFET on a semiconductor substrate of a first conductivity type, and a MIS capacitor on a first well of a second conductivity type. The MISFET includes a gate insulating film on the semiconductor substrate, a gate electrode, and a source/drain located at both sides of the gate electrode. The MIS capacitor includes a capacitor insulating film on the first well serving as a first electrode, a second electrode, and a first impurity layer of the first conductivity type. The gate electrode and the second electrode are electrically connected together, and form a floating gate. The gate insulating film and the capacitor insulating film are made of a same material, and have a same thickness. The gate electrode and the second electrode are made of a same conductive film. A second impurity layer is formed astride a border between the semiconductor substrate and the first well.


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