The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Nov. 20, 2013
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics S.a., Montrouge, FR;

Inventors:

Erwan Dornel, Fontaine, FR;

Pascal R. Tannhof, Fontainebleau, FR;

Denis Rideau, Grenoble, FR;

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/401 (2013.01); H01L 21/28247 (2013.01); H01L 29/42368 (2013.01); H01L 29/512 (2013.01); H01L 29/6659 (2013.01); H01L 29/51 (2013.01); H01L 29/7833 (2013.01); H01L 29/517 (2013.01);
Abstract

A method of fabricating a semiconductor device including providing a gate structure on a channel portion of a semiconductor substrate, wherein the gate structure includes at least one gate dielectric on the channel portion of the semiconductor substrate and at least one gate conductor on the at least one gate dielectric. An edge portion of the at least one gate dielectric is removed on each side of the gate structure, wherein the removing of the edge portion of the gate dielectric provides an exposed base edge of the at least one gate conductor and an exposed channel surface of the semiconductor substrate underlying the gate structure. The sidewall of the gate structure is oxidized, which also oxidizes at least one of the exposed base edge of the at least one gate conductor and the exposed channel surface of the semiconductor substrate that is underlying the gate structure.


Find Patent Forward Citations

Loading…