The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Nov. 03, 2011
Samuel Zafar Nawaz, Plano, TX (US);
Shaofeng Yu, Plano, TX (US);
Jeffrey E. Brighton, Dallas, TX (US);
Song Zhao, Plano, TX (US);
Samuel Zafar Nawaz, Plano, TX (US);
Shaofeng Yu, Plano, TX (US);
Jeffrey E. Brighton, Dallas, TX (US);
Song Zhao, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.