logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8927995 B1

PDFFull Text
Date of Patent:
Jan. 06, 2015

Filed:

Oct. 16, 2006

Thin film transistor with anti-diffusion area that prevents metal atoms and/or ions from source/drain electrodes from shortening the channel length and display substrate having the thin film transistor

Applicants:

Hong Koo Lee, Incheon-si, KR;

Sang Hoon Jung, Seoul, KR;

Inventors:

Hong Koo Lee, Incheon-si, KR;

Sang Hoon Jung, Seoul, KR;

Assignee:

LG Display Co., Ltd., Seoul, KR;

Attorney:

Brinks Gilson & Lione

Primary Examiner:

Phat X Cao

Assistant Examiner:

Diana C Vieira

Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 29/04 (2006.01); H01L 29/15 (2006.01); H01L 31/036 (2006.01); H01L 29/76 (2006.01); H01L 29/417 (2006.01); H01L 29/08 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78606 (2013.01); H01L 29/0657 (2013.01); H01L 29/0603 (2013.01); H01L 29/0847 (2013.01); H01L 29/78618 (2013.01);
Abstract

A thin film transistor includes a semiconductor pattern disposed on a substrate and a semiconductor pattern portion with a conductive or nonconductive characteristic, and a anti-diffusion portion on a side of the semiconductor pattern portion to prevent metal ions from being diffused along the semiconductor pattern portion. A first insulating layer covers the semiconductor pattern and has a first contact hole exposing a first region of the semiconductor pattern portion and a second contact hole exposing a second region of the semiconductor pattern portion. A gate electrode is disposed on the first insulating layer. A second insulating layer covers the gate electrode and has a third contact hole exposing the first region and a fourth contact hole exposing the second region. A source electrode is formed on the second insulating layer and connected to the first region, and a drain electrode is formed on the second insulating layer and connected to the second region.

Find Patent Forward Citations

Loading…