The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Aug. 19, 2012
Applicants:

Wen-chung Tang, Hsinchu, TW;

Fang-an Shu, Hsinchu, TW;

Yao-chou Tsai, Hsinchu, TW;

Ted-hong Shinn, Hsinchu, TW;

Inventors:

Wen-Chung Tang, Hsinchu, TW;

Fang-An Shu, Hsinchu, TW;

Yao-Chou Tsai, Hsinchu, TW;

Ted-Hong Shinn, Hsinchu, TW;

Assignee:

E Ink Holdings Inc., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/12 (2006.01); H01L 21/02 (2006.01); H01L 21/00 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); H01L 27/1259 (2013.01);
Abstract

Disclosed herein is a thin film transistor array substrate. The thin film transistor array substrate includes a display area and a non-display area. The non-display area includes a signal line, a connecting line and a metal contact. The connecting line is formed in a first patterned metal layer. The signal line and the metal contact are formed in a second patterned metal layer. The connecting line is connected to the signal line by a first through-hole, and the connecting line is connected to the metal contact by a second through-hole. Furthermore, a method of fabricating the thin film transistor array substrate is also disclosed.


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