The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
Oct. 31, 2008
Applicant:
Leslie G. Fritzemeier, Lexington, MA (US);
Inventor:
Leslie G. Fritzemeier, Lexington, MA (US);
Assignee:
Siva Power, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01); H01L 33/00 (2010.01); H01L 31/0304 (2006.01); H01L 31/0392 (2006.01); H01L 31/0693 (2012.01); H01L 31/18 (2006.01); H01L 21/02 (2006.01); H01L 33/12 (2010.01); H01S 5/02 (2006.01);
U.S. Cl.
CPC ...
H01L 33/007 (2013.01); H01L 31/0304 (2013.01); H01L 31/0392 (2013.01); H01L 31/0693 (2013.01); H01L 31/1852 (2013.01); H01L 21/02367 (2013.01); H01L 21/02491 (2013.01); H01L 21/02505 (2013.01); H01L 21/02521 (2013.01); H01L 33/12 (2013.01); H01S 5/0215 (2013.01); Y02E 10/544 (2013.01);
Abstract
Methods for forming semiconductor devices include providing a textured template, forming a buffer layer over the textured template, forming a substrate layer over the buffer layer, removing the textured template, thereby exposing a surface of the buffer layer, and forming a semiconductor layer over the exposed surface of the buffer layer.