The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2015

Filed:

Feb. 21, 2012
Applicants:

Jong-kyu Kim, Hwaseong-si, KR;

Sangsup Jeong, Suwon-si, KR;

Kukhan Yoon, Hwaseong-si, KR;

Junsoo Lee, Yongin-si, KR;

Sungii Cho, Seoul, KR;

Yong-joon Choi, Seoul, KR;

Inventors:

Jong-Kyu Kim, Hwaseong-si, KR;

Sangsup Jeong, Suwon-si, KR;

Kukhan Yoon, Hwaseong-si, KR;

Junsoo Lee, Yongin-si, KR;

SungII Cho, Seoul, KR;

Yong-Joon Choi, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 28/91 (2013.01); H01L 27/10817 (2013.01); H01L 27/10852 (2013.01); H01L 27/0203 (2013.01); H01L 21/31144 (2013.01);
Abstract

A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.


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