The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2015
Filed:
May. 12, 2011
Huiqing Pang, Newtown, PA (US);
Peter Levermore, Lambertville, NJ (US);
Emory Krall, Philadelphia, PA (US);
Kamala Rajan, Newton, PA (US);
Ruiqing (Ray) MA, Morristown, NJ (US);
Paul E. Burrows, Kennewick, WA (US);
Huiqing Pang, Newtown, PA (US);
Peter Levermore, Lambertville, NJ (US);
Emory Krall, Philadelphia, PA (US);
Kamala Rajan, Newton, PA (US);
Ruiqing (Ray) Ma, Morristown, NJ (US);
Paul E. Burrows, Kennewick, WA (US);
Universal Display Corporation, Ewing, NJ (US);
Abstract
Systems, and methods for the design and fabrication of OLEDs, including large-area OLEDs with metal bus lines, are provided. For a given panel area dimension, target luminous emittance, OLED device structure and efficiency (as given by the JVL characteristics of an equivalent small area pixel), and electrical resistivity and thickness of the bus line material and electrode onto which the bus lines are disposed, a bus line pattern may be designed such that Fill Factor (FF), Luminance Uniformity (U) and Power Loss (PL) may be optimized. One general design objective may be to maximize FF, maximize U and minimize PL. Another approach may be, for example, to define minimum criteria for U and a maximum criteria for PL, and then to optimize the bus line layout to maximize FF. OLED panels including bus lines with different resistances (R) along a length of the bus line are also described.