The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Sep. 12, 2011
Applicant:

Shinji Abe, Tokyo, JP;

Inventor:

Shinji Abe, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/20 (2006.01); G06F 11/16 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2028 (2013.01); G06F 11/1654 (2013.01); G06F 11/1645 (2013.01); G06F 11/2038 (2013.01);
Abstract

A fault-tolerant system including a plurality of modules each further including a CPU subsystem, a fault-tolerant control unit, and an I/O subsystem, wherein the fault-tolerant control unit includes a master FT control LSI chip and at least one slave FT control LSI chip. One module is placed in an active state while the other module is placed in a standby state, so that I/O requests made by CPU subsystems of these modules are selectively delivered to I/O subsystems based on the master/slave relationship. Upon receiving fault information representing a failed subsystem which is either the CPU subsystem or the I/O subsystem found in the module, the master FT control LSI chip sends a command for controlling isolation of the failed subsystem to the slave FT control LSI chip, so that the slave FT control LSI chip controls isolation of the failed subsystem based on the command.


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