The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2014

Filed:

Aug. 31, 2011
Applicants:

Yasushi Sasaki, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Etsuo Yamamoto, Osaka, JP;

Inventors:

Yasushi Sasaki, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Etsuo Yamamoto, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/00 (2006.01); H03K 3/02 (2006.01); G11C 19/18 (2006.01); G11C 19/28 (2006.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
H03K 3/02 (2013.01); G11C 19/184 (2013.01); G11C 19/28 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A flip-flop of the present invention includes: an input terminal; an output terminal; a first control signal terminal and a second control signal terminal; a first output section including a bootstrap capacitor, the first output section being connected to the first control signal terminal and the output terminal; a second output section connected to a first output section source and the output terminal; a first input section connected to the input terminal, the first input section charging the bootstrap capacitor; a discharge section discharging the bootstrap capacitor; a second input section connected to the input terminal, the second input section being also connected to the second output section; a reset section controlling the discharge section and the second output section, the reset section being connected to the second control signal terminal; a first initialization section controlling the first output section; a second initialization section controlling the first input section; and a third initialization section controlling the discharge section and the second output section. This makes it possible to realize a shift register capable of performing an all-ON operation regardless of clock signals.


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